This invention relates generally to reducing the amount of power consumed in a reduced dynamic power consumption state by a variety of electronic devices including those that use battery power sources, such as portable computers.
In devices such as computers that may be operated from a battery, it is important to reduce the power consumption to the greatest possible extent. The usefulness of battery operated devices is reduced if the battery must be recharged frequently. A variety of techniques are known for reducing the dynamic power consumption. For example the Advanced Configuration and Power Interface (ACPI) Specification, (Rev. 1.0, Dec. 22, 1996) sets forth information about how to reduce the dynamic power consumption of portable and other computer systems.
With respect to the microprocessors used in computer systems, four processor power consumption states (C0-C3) are defined in the ACPI Specification. When the processor is executing instructions it is in a C0 state. There are three non-executing states (C1-C3). In a working computer system, the operating system dynamically transitions idle processors into the appropriate power consumption state.
State C1 is the processor power state with the lowest latency. Basically, aside from putting the processor in a non-executing power state, the C1 state has no other software visible effects.
The C2 power state offers improved power savings over the C1 state. Like the C1 state, aside from putting the processor in a non-executing power state, the state has no other software visible effects. In the C2 power state, the processor is still able to maintain the context of the system caches.
The C3 power state offers still lower dynamic power consumption compared to the C1 and C2 states. While in the C3 state, the processor""s caches are maintained but snoops are ignored. The operating system software is responsible for ensuring that cache coherency is maintained. In the C3 state, the processor may not be able to maintain coherency of the processor caches with respect to other system activities. The C3 power consumption state uses less power but has a higher exit latency than the C2 power state.
Generally, the C3 state uses one of two mechanisms to maintain cache coherency. The operating system may flush and invalidate the caches prior to entering the C3 state. The flushing of the caches may be provided through predefined ACPI mechanisms. Alternatively hardware mechanisms may be provided to prevent bus masters from writing to memory. In processors that use hardware mechanisms, the bus masters may be disabled prior to entering the C3 state. When a bus master requests an access, the processor awakens from the C3 state and re-enables bus master access.
While the reduced power consumption states outlined by the ACPI Specification and known techniques have many advantages, there are instances where greater power consumption reductions may be desired. Thus, there is a continuing need for ways to further reduce the power consumption of computer systems and other components including devices which are operated from batteries.
In accordance with one embodiment, a method of reducing the power consumed by an electronic device using a clock signal includes disabling the clock signal and reducing the leakage power consumption of the device.